Manuscript Number : IJSRST52310512

Area Efficient Approximate Multiplier Using 4 : 2 Compressors with Improved Accuracy

Authors(2) :-Sanga Ramya, Pandiri Padma

Fast implementations based on approximation technology have revolutionized the field of circuit design, enabling the development of high-performance and fault-tolerant circuits. However, this increased performance often comes at the cost of reduced accuracy, which may not be critical for many applications. They are notably required in a variety of settings since these methods also attempt to reduce system complexity, latency, and power consumption.In order to reduce size, latency, and power consumption while retaining a same level of accuracy, the aim of this project is to create and test an approximation compressor. In comparison to a precise 4:2 compressor, the suggested 4:2 compressor approximation has a noticeably smaller footprint, less power loss, and lower latency. Dadda multipliers in 8-bit and 16-bit can be easily produced with these upgraded compressors.These Dadda multipliers, constructed with the improved compressors, offer a similar level of precision as modern approximation multipliers. With no reduction in computation accuracy, this results in an improvement in total performance.

Authors and Affiliations

Sanga Ramya
M.E Scholar, Embedded systems and VLSI design specialization, Department of ECE, @Osmania University, Hyderabad, India
Pandiri Padma
Assistant professor, Department of Electronics and communication Engineering, @Osmania University, Hyderabad, India

Approx. 4:2 Compressors, Approx. Multipliers.

  1. Voltage scalable high-speed robust hybrid arithmetic units utilising adaptive clocking, a paper by Mohapatra et al., was published in an IEEE transaction in 2010.
  2. Multiplier structures for low power applications in deep CMOS published by Baran et al. in IEEE ISCAS in May 2011.
  3. A overview of approximation computing approaches was the subject of a report by S. Mittal that was presented at ACM in March 2016.
  4. Liu et al. conducted an analysis of the 2017 study A review categorization and comparative evaluation of approximate arithmetic circuits.
  5. In September 2013, Lombardi and his group of researchers published a transaction study in IEEE titled "New metrics for the reliability of approximate and probabilistic adders."
  6. Energy-efficient approximate multiplication for digital signal processing and classification applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1180-1184, June 2015. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim.
  7. Hybrid approximate multiplier architectures for enhanced power-accuracy trade-offs, by G. Zervakis, S. Xydis, K. Tsoumanis, D. Soudris, and K. Pekmestzi, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des. (ISLPED), Rome, Italy, July 2015, pp. 79-84.
  8. B. Shao and P. Li, Array-based approximate arithmetic computing: A general model and applications to multiplier and squarer design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 4, pp. 1081–1090, Apr. 2015.
  9. C.-H. Chang, J. Gu, and M. Zhang, Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1985–1997, Oct. 2004

Publication Details

Published in : Volume 10 | Issue 5 | September-October 2023
Date of Publication : 2023-09-11
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 99-107
Manuscript Number : IJSRST52310512
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Sanga Ramya, Pandiri Padma, " Area Efficient Approximate Multiplier Using 4 : 2 Compressors with Improved Accuracy", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 10, Issue 5, pp.99-107, September-October-2023.
Journal URL : https://ijsrst.com/IJSRST52310512
Citation Detection and Elimination     |      | |
  • Energy-efficient approximate multiplication for digital signal processing and classification applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1180-1184, June 2015. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim.
  • Hybrid approximate multiplier architectures for enhanced power-accuracy trade-offs, by G. Zervakis, S. Xydis, K. Tsoumanis, D. Soudris, and K. Pekmestzi, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des. (ISLPED), Rome, Italy, July 2015, pp. 79-84.
  • B. Shao and P. Li, Array-based approximate arithmetic computing: A general model and applications to multiplier and squarer design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 4, pp. 1081–1090, Apr. 2015.
  • C.-H. Chang, J. Gu, and M. Zhang, Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1985–1997, Oct. 2004
    • " target="_blank"> BibTeX     |
  • Energy-efficient approximate multiplication for digital signal processing and classification applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1180-1184, June 2015. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim.
  • Hybrid approximate multiplier architectures for enhanced power-accuracy trade-offs, by G. Zervakis, S. Xydis, K. Tsoumanis, D. Soudris, and K. Pekmestzi, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des. (ISLPED), Rome, Italy, July 2015, pp. 79-84.
  • B. Shao and P. Li, Array-based approximate arithmetic computing: A general model and applications to multiplier and squarer design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 4, pp. 1081–1090, Apr. 2015.
  • C.-H. Chang, J. Gu, and M. Zhang, Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1985–1997, Oct. 2004
    • " target="_blank">RIS     |
  • Energy-efficient approximate multiplication for digital signal processing and classification applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1180-1184, June 2015. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim.
  • Hybrid approximate multiplier architectures for enhanced power-accuracy trade-offs, by G. Zervakis, S. Xydis, K. Tsoumanis, D. Soudris, and K. Pekmestzi, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des. (ISLPED), Rome, Italy, July 2015, pp. 79-84.
  • B. Shao and P. Li, Array-based approximate arithmetic computing: A general model and applications to multiplier and squarer design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 4, pp. 1081–1090, Apr. 2015.
  • C.-H. Chang, J. Gu, and M. Zhang, Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1985–1997, Oct. 2004
    • " target="_blank">CSV

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