Manuscript Number : IJSRST2310116
Implementation of Novel Approximate Adder Using Parallel Prefix Structure
Authors(2) :-G Indra Kumar, Dr. B. Sudharani This article offers a unique approximation adder which uses error-reduced carry prediction and constant reduction in conjunction with error reduction techniques. The suggested adder design actually improve computing accuracy while also improving hardware effectiveness. In comparison to the approximate adders studied in this research, the proposed carry forecast technique can elevate prediction error rates. The error reduction technique also enhances overall computation efficiency by lowering the error distance (ED). The suggested adder is one of the most economical because it has the effective design compromise of the adders beneath analysis. We also show that whenever the postulated adder is used in application areas such as digital image processing and machine learning, the approximation errors caused by the adder have even less influence on quality attributes.
G Indra Kumar Error Distance, Approximate Adder.
Publication Details
Published in : Volume 10 | Issue 1 | January-February 2023 Article Preview
M.Tech, Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Tirupati, India.
Dr. B. Sudharani
Associate Professor, Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Tirupati, India.
Date of Publication : 2023-02-28
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 151-158
Manuscript Number : IJSRST2310116
Publisher : Technoscience Academy
Journal URL : https://ijsrst.com/IJSRST2310116
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