Manuscript Number : IJSRST196493

Design Implementation of Successive Approximation Register A/D Converter

Authors(1) :-Dr. Priyesh P. Gandhi

This paper presents design implementation of Successive Approximation Register ADC. The ADC is the main building block in modem signal processing and communication systems. Main purpose of the ADC is to convert analog input into an equivalent digital output. There are many ADCs depending on the application like Sigma Delta ADC, Pipelined ADC, SAR ADC. The Successive Approximation Register (SAR) ADC is the most widely used converter in industrial control applications. It has good ratio of speed/power and has compact size that make this converter into an inexpensive device. A low power 8-bit 200MS/s Successive Approximation Register Analog to Digital Converter is designed and implemented in 180nm TSMC CMOS VLSI process. To reduce the complexity of design TG based D Flip-flop and charge scaling DAC are used. To increase the conversion rate and reduce the overall power dissipation of ADC Dynamic Latch Comparator is used.

Authors and Affiliations

Dr. Priyesh P. Gandhi
Principal, Sigma Institute of Engineering, Vadodara, Gujarat, India

Analog to Digital Converters (ADCs), Successive Approximation (SAR), Flash ADC, Propagation delay, Offset Voltage, Power Dissipation Spurious Free Dynamic Range (SFDR).

  1. Xiong Zhou and Qiang Li "A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS" 978-1-4673-1556-2/12/$31.00@2012 IEEE
  2. In the year 2014, Babita Diana K, and D. lackuline Moni Presented, "An Ultra Low Power 8 Bit SAR ADC Suitable for Wireless Medical Applications" International Conference on Communication and Signal Processing, April 3-5, 2014, India, 978-1-4799-3358-7114/$31.00 ©2014 IEEE
  3. Umamaheswari.V.S.1, Rajaramya.V.G2 "Low Power High Performance Doubletail Comparator" ,IJSET@2014
  4. Yafei Ye, Liyuan Liu, Fule Li, Dongmei Li, Zhihua Wang "An 8-bit 1MHz Successive Approximation Register A/D with 7.98 ENOB" 978-1-61284-632-3/11/$26.00 ©2011 IEEE
  5. Chung-Yi Li, Chih-Wen Lu, Hao-Tsun Chao, Chin Hsia "A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array"
  6. Jing Yang, Thura Lin Naing, Bob Brodersen "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS"
  7. Ryota Sekimoto, Akira Shikata, and Hiroki Ishikuro "A Power Scalable SAR-ADC in 0.18μm-CMOS with 0.5V Nano-Watt Operation" 2011 1st International Symposium on Access Spaces (ISAS), IEEE-ISAS 2011
  8. Masoume Akbari and Mohammad Maymandi-Nejad, S. Abdollah Mirbozorgi "A New Rail-to-Rail Ultra Low Voltage High Speed Comparator" 978-1-4673-5634-3/13/$31.00 ©2013 IEEE
  9. ALGN Aditya, G.Rakesh Chowdary, J.Meenakshi ,T.Praveen Blessington , M.S.Vamsi Krishna "Implementation ff Low Power Successive Approximation ADC for MAV'S" 978-1-4673-4862-1/13/$31.00 ©2013 IEEE
  10. Hur A. Hassan, Izhal Abdul Halin, Ishak Bin Aris , Mohd Khair Bin Hassan Presented, "Design of A Low Power 8-bit SAR-ADC CMOS" Proceedings of 2009 Student Conference on Research and Development (SCOReD 2009),16-18 Nov. 2009, UPM Serdang, Malaysia
  11. Meghana Kulkarni, Muttappa Shingadi, G.H. Kulkarni, "6-Bit Charge Scaling DAC and SAR ADC", IJAREEIE Vol. 3, Issue 12, December 2014
  12. Rabeeh Majidi, "Low Power Design of Successive Approximation Registers" Worcester MA USA
  13. Byung-Geun Lee, "Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 10.1109/TVLSI.2014.2331354
  14. R. Jecob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout and Simulation", IEEE Press Series on Microelectronic Systems, 1997, pp.755-837.
  15. Phillip E. Allen, Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press, Second Edition, 2002, pp.439-491.
  16. Sung- Mo Kang, Yusuf Leblebici, " CMOS Digital Integrated Cicuits", McGrow – Hill Higher Education, Second edition, 2003.
  17. M. Morris Manno,"DIGITAL DESIGN" , Third Edition.
  18. Venkataraman Radhakrishnan, "Design of a low power analog to digital converter in a 130nm CMOS technology", Thesis LiTH-ISY-EX--11/4532—SE Linköping 2011/12/05
  19. Bharti Chaudhri, "Development of High Performance Pipelined ADC", Thesis Gujarat Technological University, Department of Electronics and communication Engineering, May-2014.
  20. Dai Zhang, "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC", LiTH-ISY-EX--09/4176--SE Linköping, March

Publication Details

Published in : Volume 6 | Issue 3 | May-June 2019
Date of Publication : 2019-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 335-344
Manuscript Number : IJSRST196493
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Dr. Priyesh P. Gandhi, " Design Implementation of Successive Approximation Register A/D Converter ", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 6, Issue 3, pp.335-344, May-June-2019.
Journal URL : https://ijsrst.com/IJSRST196493
Citation Detection and Elimination     |      | |
  • In the year 2014, Babita Diana K, and D. lackuline Moni Presented, "An Ultra Low Power 8 Bit SAR ADC Suitable for Wireless Medical Applications" International Conference on Communication and Signal Processing, April 3-5, 2014, India, 978-1-4799-3358-7114/$31.00 ©2014 IEEE
  • Umamaheswari.V.S.1, Rajaramya.V.G2 "Low Power High Performance Doubletail Comparator" ,IJSET@2014
  • Yafei Ye, Liyuan Liu, Fule Li, Dongmei Li, Zhihua Wang "An 8-bit 1MHz Successive Approximation Register A/D with 7.98 ENOB" 978-1-61284-632-3/11/$26.00 ©2011 IEEE
  • Chung-Yi Li, Chih-Wen Lu, Hao-Tsun Chao, Chin Hsia "A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array"
  • Jing Yang, Thura Lin Naing, Bob Brodersen "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS"
  • Ryota Sekimoto, Akira Shikata, and Hiroki Ishikuro "A Power Scalable SAR-ADC in 0.18μm-CMOS with 0.5V Nano-Watt Operation" 2011 1st International Symposium on Access Spaces (ISAS), IEEE-ISAS 2011
  • Masoume Akbari and Mohammad Maymandi-Nejad, S. Abdollah Mirbozorgi "A New Rail-to-Rail Ultra Low Voltage High Speed Comparator" 978-1-4673-5634-3/13/$31.00 ©2013 IEEE
  • ALGN Aditya, G.Rakesh Chowdary, J.Meenakshi ,T.Praveen Blessington , M.S.Vamsi Krishna "Implementation ff Low Power Successive Approximation ADC for MAV'S" 978-1-4673-4862-1/13/$31.00 ©2013 IEEE
  • Hur A. Hassan, Izhal Abdul Halin, Ishak Bin Aris , Mohd Khair Bin Hassan Presented, "Design of A Low Power 8-bit SAR-ADC CMOS" Proceedings of 2009 Student Conference on Research and Development (SCOReD 2009),16-18 Nov. 2009, UPM Serdang, Malaysia
  • Meghana Kulkarni, Muttappa Shingadi, G.H. Kulkarni, "6-Bit Charge Scaling DAC and SAR ADC", IJAREEIE Vol. 3, Issue 12, December 2014
  • Rabeeh Majidi, "Low Power Design of Successive Approximation Registers" Worcester MA USA
  • Byung-Geun Lee, "Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 10.1109/TVLSI.2014.2331354
  • R. Jecob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout and Simulation", IEEE Press Series on Microelectronic Systems, 1997, pp.755-837.
  • Phillip E. Allen, Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press, Second Edition, 2002, pp.439-491.
  • Sung- Mo Kang, Yusuf Leblebici, " CMOS Digital Integrated Cicuits", McGrow – Hill Higher Education, Second edition, 2003.
  • M. Morris Manno,"DIGITAL DESIGN" , Third Edition.
  • Venkataraman Radhakrishnan, "Design of a low power analog to digital converter in a 130nm CMOS technology", Thesis LiTH-ISY-EX--11/4532—SE Linköping 2011/12/05
  • Bharti Chaudhri, "Development of High Performance Pipelined ADC", Thesis Gujarat Technological University, Department of Electronics and communication Engineering, May-2014.
  • Dai Zhang, "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC", LiTH-ISY-EX--09/4176--SE Linköping, March
    • " target="_blank"> BibTeX     |
  • In the year 2014, Babita Diana K, and D. lackuline Moni Presented, "An Ultra Low Power 8 Bit SAR ADC Suitable for Wireless Medical Applications" International Conference on Communication and Signal Processing, April 3-5, 2014, India, 978-1-4799-3358-7114/$31.00 ©2014 IEEE
  • Umamaheswari.V.S.1, Rajaramya.V.G2 "Low Power High Performance Doubletail Comparator" ,IJSET@2014
  • Yafei Ye, Liyuan Liu, Fule Li, Dongmei Li, Zhihua Wang "An 8-bit 1MHz Successive Approximation Register A/D with 7.98 ENOB" 978-1-61284-632-3/11/$26.00 ©2011 IEEE
  • Chung-Yi Li, Chih-Wen Lu, Hao-Tsun Chao, Chin Hsia "A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array"
  • Jing Yang, Thura Lin Naing, Bob Brodersen "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS"
  • Ryota Sekimoto, Akira Shikata, and Hiroki Ishikuro "A Power Scalable SAR-ADC in 0.18μm-CMOS with 0.5V Nano-Watt Operation" 2011 1st International Symposium on Access Spaces (ISAS), IEEE-ISAS 2011
  • Masoume Akbari and Mohammad Maymandi-Nejad, S. Abdollah Mirbozorgi "A New Rail-to-Rail Ultra Low Voltage High Speed Comparator" 978-1-4673-5634-3/13/$31.00 ©2013 IEEE
  • ALGN Aditya, G.Rakesh Chowdary, J.Meenakshi ,T.Praveen Blessington , M.S.Vamsi Krishna "Implementation ff Low Power Successive Approximation ADC for MAV'S" 978-1-4673-4862-1/13/$31.00 ©2013 IEEE
  • Hur A. Hassan, Izhal Abdul Halin, Ishak Bin Aris , Mohd Khair Bin Hassan Presented, "Design of A Low Power 8-bit SAR-ADC CMOS" Proceedings of 2009 Student Conference on Research and Development (SCOReD 2009),16-18 Nov. 2009, UPM Serdang, Malaysia
  • Meghana Kulkarni, Muttappa Shingadi, G.H. Kulkarni, "6-Bit Charge Scaling DAC and SAR ADC", IJAREEIE Vol. 3, Issue 12, December 2014
  • Rabeeh Majidi, "Low Power Design of Successive Approximation Registers" Worcester MA USA
  • Byung-Geun Lee, "Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 10.1109/TVLSI.2014.2331354
  • R. Jecob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout and Simulation", IEEE Press Series on Microelectronic Systems, 1997, pp.755-837.
  • Phillip E. Allen, Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press, Second Edition, 2002, pp.439-491.
  • Sung- Mo Kang, Yusuf Leblebici, " CMOS Digital Integrated Cicuits", McGrow – Hill Higher Education, Second edition, 2003.
  • M. Morris Manno,"DIGITAL DESIGN" , Third Edition.
  • Venkataraman Radhakrishnan, "Design of a low power analog to digital converter in a 130nm CMOS technology", Thesis LiTH-ISY-EX--11/4532—SE Linköping 2011/12/05
  • Bharti Chaudhri, "Development of High Performance Pipelined ADC", Thesis Gujarat Technological University, Department of Electronics and communication Engineering, May-2014.
  • Dai Zhang, "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC", LiTH-ISY-EX--09/4176--SE Linköping, March
    • " target="_blank">RIS     |
  • In the year 2014, Babita Diana K, and D. lackuline Moni Presented, "An Ultra Low Power 8 Bit SAR ADC Suitable for Wireless Medical Applications" International Conference on Communication and Signal Processing, April 3-5, 2014, India, 978-1-4799-3358-7114/$31.00 ©2014 IEEE
  • Umamaheswari.V.S.1, Rajaramya.V.G2 "Low Power High Performance Doubletail Comparator" ,IJSET@2014
  • Yafei Ye, Liyuan Liu, Fule Li, Dongmei Li, Zhihua Wang "An 8-bit 1MHz Successive Approximation Register A/D with 7.98 ENOB" 978-1-61284-632-3/11/$26.00 ©2011 IEEE
  • Chung-Yi Li, Chih-Wen Lu, Hao-Tsun Chao, Chin Hsia "A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array"
  • Jing Yang, Thura Lin Naing, Bob Brodersen "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS"
  • Ryota Sekimoto, Akira Shikata, and Hiroki Ishikuro "A Power Scalable SAR-ADC in 0.18μm-CMOS with 0.5V Nano-Watt Operation" 2011 1st International Symposium on Access Spaces (ISAS), IEEE-ISAS 2011
  • Masoume Akbari and Mohammad Maymandi-Nejad, S. Abdollah Mirbozorgi "A New Rail-to-Rail Ultra Low Voltage High Speed Comparator" 978-1-4673-5634-3/13/$31.00 ©2013 IEEE
  • ALGN Aditya, G.Rakesh Chowdary, J.Meenakshi ,T.Praveen Blessington , M.S.Vamsi Krishna "Implementation ff Low Power Successive Approximation ADC for MAV'S" 978-1-4673-4862-1/13/$31.00 ©2013 IEEE
  • Hur A. Hassan, Izhal Abdul Halin, Ishak Bin Aris , Mohd Khair Bin Hassan Presented, "Design of A Low Power 8-bit SAR-ADC CMOS" Proceedings of 2009 Student Conference on Research and Development (SCOReD 2009),16-18 Nov. 2009, UPM Serdang, Malaysia
  • Meghana Kulkarni, Muttappa Shingadi, G.H. Kulkarni, "6-Bit Charge Scaling DAC and SAR ADC", IJAREEIE Vol. 3, Issue 12, December 2014
  • Rabeeh Majidi, "Low Power Design of Successive Approximation Registers" Worcester MA USA
  • Byung-Geun Lee, "Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 10.1109/TVLSI.2014.2331354
  • R. Jecob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout and Simulation", IEEE Press Series on Microelectronic Systems, 1997, pp.755-837.
  • Phillip E. Allen, Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press, Second Edition, 2002, pp.439-491.
  • Sung- Mo Kang, Yusuf Leblebici, " CMOS Digital Integrated Cicuits", McGrow – Hill Higher Education, Second edition, 2003.
  • M. Morris Manno,"DIGITAL DESIGN" , Third Edition.
  • Venkataraman Radhakrishnan, "Design of a low power analog to digital converter in a 130nm CMOS technology", Thesis LiTH-ISY-EX--11/4532—SE Linköping 2011/12/05
  • Bharti Chaudhri, "Development of High Performance Pipelined ADC", Thesis Gujarat Technological University, Department of Electronics and communication Engineering, May-2014.
  • Dai Zhang, "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC", LiTH-ISY-EX--09/4176--SE Linköping, March
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